Sort by
Refine Your Search
-
Listed
-
Category
-
Country
-
Program
-
Employer
- Carnegie Mellon University
- UNIVERSIDAD POLITECNICA DE MADRID
- California State University San Marcos
- The California State University
- Fraunhofer-Gesellschaft
- Universidade de Vigo
- Oak Ridge National Laboratory
- Universitat Politècnica de Catalunya (UPC)- BarcelonaTECH
- Eindhoven University of Technology (TU/e)
- European Space Agency
- Nature Careers
- VIETNAMESE-GERMAN UNIVERSITY
- CNRS
- Delft University of Technology (TU Delft); yesterday published
- GSI Helmholtzzentrum für Schwerionenforschung
- IMEC
- International Iberian Nanotechnology Laboratory (INL)
- Nantes Université
- Nanyang Technological University
- RMIT University
- Radix Trading LLC
- SUNY Oswego
- The University of Western Australia
- University of Birmingham
- University of Cyprus
- University of Siegen
- University of Southern Denmark
- University of Texas at Austin
- Universität Siegen
- 19 more »
- « less
-
Field
-
, such as C or C++, into hardware description languages like Verilog or VHDL. This enables designers to create digital hardware (e.g., ASICs or FPGAs) more efficiently, by working at a higher abstraction
-
reliability, or fault-mitigation techniques. Strong programming skills (C/C++, Python; hardware-description languages “e.g., HLS, VHDL” is a plus). Motivation to pursue a PhD and contribute to applied AI
-
. Knowledge, Skills, and Abilities: Experience with modern software languages such as Python and C/C++, and hardware design languages including Verilog, VHDL, or other HLS languages Familiarity with software
-
, Digital signal Processing (punctuation: 25) Item 03: Experience in: RF design for satellite comm, FPGA programming in VHDL., PCB design for RF (punctuation: 25) Item 04: Personal interview. The interview
-
. Knowledge, Skills, and Abilities: Experience with modern software languages such as Python and C/C++, and hardware design languages including Verilog, VHDL, or other HLS languages Familiarity with software
-
. Knowledge, Skills, and Abilities: Experience with modern software languages such as Python and C/C++, and hardware design languages including Verilog, VHDL, or other HLS languages Familiarity with software
-
with fault detection, system reliability, or fault-mitigation techniques. Strong programming skills (C/C++, Python; hardware-description languages “e.g., HLS, VHDL” is a plus). Motivation to pursue a PhD
-
criteria - Master simulation tools such as SPICE, VHDL(-AMS), Cadence, as well as calculation and modeling tools such as Matlab/Octave or Python. Skills in finite-element type numerical simulation will be a
-
, microarchitecture, and hardware/software co-design. Experience with RTL design (Verilog/SystemVerilog/VHDL) and integrating TLM with RTL for hybrid simulation environments is a plus. Familiarity with standard
-
sistemas embebidos y VHDL; Programación en C/C++ y/o Python; Conocimiento sobre VHDL y/o SystemVerilog. Un nivel alto de inglés, así como estar dispuesto a aprender español, también son necesarios para este