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using state-of-the-art techniques. Develop bytecode to test and analyze VHDL for FPGAs and ensure hardware interfaces and controls meet the intended design. Who you are You have a BS with three (3) years
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using state-of-the-art techniques. Develop bytecode to test and analyze VHDL for FPGAs and ensure hardware interfaces and controls meet the intended design. Who you are You have a BS with 10 years
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Max Planck Institute of Molecular Cell Biology and Genetics, Dresden | Dresden, Sachsen | Germany | 2 months ago
hardware description language (VHDL, Verilog, …). Our offer Salary corresponding to qualification and experience according to TVöD Bund (German civil service tariff). The initial contract is for 2 years with
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-level knowledge in FPGA/hardware design using hardware description languages and/or high-level synthesis (VHDL, Verilog, Vitis HLS, Vitis), and experience in programming FPGA boards. You have basic
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VHDL [25%] Help optimize readout systems to enable more sensitive and larger format sensor and readout circuits, including optimization of the signal to noise of the microwave readout room-temperature
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international degree Preferred qualifications PhD in Astronomy, Physics, or Electrical Engineering. Expertise in electronic circuit design Proficiency with: Linux, Python, C, Verilog, VHDL, CUDA, MATLAB, and
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, JavaScript, VHDL Immediate availability EVALUATION CRITERIA The selection will be based on the following criteria: Academic record – 40% Past Experience in Distribution Systems, Optimisation and Control – 30
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sponsorship of an employment visa for this opportunity. Knowledge, Skills, and Abilities A published track record of conducting research and applying scientific methods. Mastery of C/C++, Python, Verilog/VHDL
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knowledge in the fields of power electronics, electrical machines & drives and control theory/engineering Excellent skills in Python, MATLAB and VHDL (FPGA) Excellent command of English (at least C1 level) is
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sponsorship of an employment visa for this opportunity. Knowledge, Skills, and Abilities A published track record of conducting research and applying scientific methods. Mastery of C/C++, Python, Verilog/VHDL