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accelerator applications, especially storage ring lattice and orbit control. Proficient in RTL design (Verilog/SystemVerilog/VHDL), IP integration, simulation, timing closure, and FPGA deployment. Skilled in C
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board (PCB) design, analog and digital telecommunications, advanced digital design, wireless networks, VLSI, VHDL, FPGA or a closely related field. Must be able to teach related coursework in electronics
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mitigate those that emerge. Analyze FPGA hardware and software interface specifications described via VHDL or Verilog to ensure it meets system requirements. Analyze software test and evaluation techniques
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interface specifications described via VHDL or Verilog to ensure it meets system requirements. Analyze software test and evaluation techniques and methodologies. Analyze static, dynamic and complexity
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prohibited from hiring employees to perform CSU-related work outside California. Working in the State of California is a condition of employment. Preferred qualifications: Teaching experience with VHDL
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using a hardware description language (such as VHDL), test bench development, and implementation of advanced digital design systems in the laboratory component. Minimum qualifications: A master's degree
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mitigate those that emerge. Analyze FPGA hardware and software interface specifications described via VHDL or Verilog to ensure it meets system requirements. Analyze software test and evaluation techniques
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that emerge. Analyze FPGA hardware and software interface specifications described via VHDL or Verilog to ensure it meets system requirements. Analyze software test and evaluation techniques and methodologies
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FPGA hardware and software interface specifications described via VHDL or Verilog to ensure it meets system requirements. Analyze software test and evaluation techniques and methodologies. Analyze static
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mitigate those that emerge. Analyze FPGA hardware and software interface specifications described via VHDL or Verilog to ensure it meets system requirements. Analyze software test and evaluation techniques