Sort by
Refine Your Search
-
Listed
-
Category
-
Country
-
Program
-
Employer
- Carnegie Mellon University
- Fraunhofer-Gesellschaft
- Pennsylvania State University
- Brookhaven Lab
- National University of Singapore
- The University of Queensland
- Lawrence Berkeley National Laboratory
- Technical University of Denmark
- ;
- Autonomous University of Madrid (Universidad Autónoma de Madrid)
- Battelle
- California State University San Marcos
- Delft University of Technology (TU Delft)
- Forschungszentrum Jülich
- International Iberian Nanotechnology Laboratory (INL)
- Johnson & Wales University
- Macquarie University
- Manchester Metropolitan University
- Max Planck Institute of Molecular Cell Biology and Genetics, Dresden
- North Carolina State University
- Princeton University
- Radix Trading LLC
- University of California
- University of Delaware
- University of Michigan
- Virginia Tech
- Yale University
- 17 more »
- « less
-
Field
-
, or Matlab/Octave. Strong written and verbal communication skills. Experienced professional with expertise in RTL design (Verilog, SystemVerilog, VHDL), IP integration, simulation, timing closure, and hardware
-
hardware description language such as Chisel, VDHL, or Verilog. Knowing Chisel is a bonus. Knowledge of real-time systems System programming in C You must have a two-year master's degree (120 ECTS points
-
qualification, you must hold a PhD degree (or equivalent) in computer science, computer engineering, or electrical engineering. Hardware design in a hardware description language such as Chisel, VDHL, or Verilog
-
California State University San Marcos | San Marcos, California | United States | about 15 hours ago
or Verilog Programming for Xilinx, or an engineering class Electrical Engineering industry or research experience Experience with ABET reporting Demonstrated commitment to actively engaging undergraduates in
-
of embedded machine learning, neuromorphic hardware and deep learning accelerators. Want to get more information? Click here. What you will do Responsible for RTL design (VHDL, Verilog) of digital blocks and
-
towards a better solution > Proficiency with Python for unit testing > Experience coding in VHDL /verilog > Used Xilnix and/or Altera FPGAs > Familiar with Modelsim > Previously worked on large FPGA stratix
-
experience includes using MATLAB, GNU Radio, HDL Coder, REDHAWK, XMIDAS, VHDL/Verilog, C++, and/or Python for RF spectrum access applications. (2) Foundation in quantum mechanics, with additional emphases
-
circuit design experience preferred Know how to design circuit using one or more of the software listed (Cadence; Fluent use of LT-Spice, Verilog-A, Python, ADS, ICCAP, etc.) Know how to perform circuit
-
. Specific requirements of the candidate Applicants should have a strong background in cryptography, FPGA design, or embedded systems. Experience with hardware design (e.g., Verilog/VHDL), post-quantum
-
with MATLAB (by MathWorks) computing environment Desirable skills : Proficient in Verilog programming and simulation. Experienced in Verilog regression testing, including the development, execution, and