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Field
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-Level Synthesis (HLS) implementations. Working knowledge of C++/C, Python, Verilog. Motivated self-starter with the ability to work independently and to participate creatively in collaborative teams
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++. Experience in RTL design and FPGA prototyping using VHDL/Verilog and/or HLS tools is highly desirable A research-oriented attitude along with a result-focused mindset. Ability to work in a collaborative
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. Demonstrated programming experience in Python and C/C++ or Verilog, SystemVerilog. Excellent oral and written communication skills. Ability to work productively independently and collaboratively as part of a
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Python and C/C++ or Verilog, SystemVerilog. Excellent oral and written communication skills. Ability to work productively independently and collaboratively as part of a multidisciplinary team. Desired
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field. Solid background in digital IC design and digital signal processing. Hands-on RTL design skills (SystemVerilog / Verilog / VHDL) plus scripting (Python / MATLAB / C/C++). Strong command of English
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++ programming languages and data analysis techniques General knowledge of microelectronics and FPGAs (VHDL or Verilog) is desirable Knowledge in radiation physics and dosimetry Interdisciplinary collaboration
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hardware description languages (HDLs) such as Verilog or VHDL Strong understanding of digital design principles and embedded systems Proficiency in low-level programming languages such as C, Rust and RISC-V
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accelerator applications, especially storage ring lattice and orbit control. Proficient in RTL design (Verilog/SystemVerilog/VHDL), IP integration, simulation, timing closure, and FPGA deployment. Skilled in C
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Engineering, or Computer Science, with relevant industrial or academic experience in digital hardware design, system modeling, and/or uArchitecture research. You are experienced in RTL design flows (Verilog
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to an international team a strong background in one or more of the following areas: field programmable gate arrays (FPGAs), hardware description languages (e.g. VHDL or Verilog), high-level synthesis (HLS), artificial