Sort by
Refine Your Search
-
Listed
-
Category
-
Country
-
Program
-
Employer
- Carnegie Mellon University
- National University of Singapore
- Pennsylvania State University
- Brookhaven Lab
- Fraunhofer-Gesellschaft
- The University of Queensland
- Delft University of Technology (TU Delft)
- Ghent University
- UNIVERSIDAD POLITECNICA DE MADRID
- University of Southern California
- ; Manchester Metropolitan University
- Autonomous University of Madrid (Universidad Autónoma de Madrid)
- Battelle
- Forschungszentrum Jülich
- INESC ID
- Inria, the French national research institute for the digital sciences
- International Iberian Nanotechnology Laboratory (INL)
- Johnson & Wales University
- Lawrence Berkeley National Laboratory
- Macquarie University
- Manchester Metropolitan University
- Max Planck Institute of Molecular Cell Biology and Genetics, Dresden
- National University of Science and Technology POLITEHNICA Bucharest
- Princeton University
- Purdue University
- Radboud University
- Radix Trading LLC
- Sheffield Hallam University
- Ulster University
- University of Birmingham
- University of California Berkeley
- University of Delaware
- University of Texas at Austin
- University of Twente (UT)
- Virginia Tech
- Warsaw University of Technology
- Woods Hole Oceanographic Institution
- Yale University
- 28 more »
- « less
-
Field
-
., RS-485, CAN bus communications); Experience in FPGA design flow (i.e., VHLD or Verilog synthesis) Experience in generic analog front-end design for sensors (i.e., Capacitive, Resistive or Optical
-
charge pump topologies at 4k. Behavioural modelling in Verilog-A. Transistor level design and verification through simulation. Layout of the charge pump and post layout verification. Documentation and
-
-level knowledge in FPGA/hardware design using hardware description languages and/or high-level synthesis (VHDL, Verilog, Vitis HLS, Vitis), and experience in programming FPGA boards. You have basic
-
Understanding of the hardware/chip development flow Knowledge of electronics, or digital design (VHDL/Verilog) or analogue/RF design Appointment Type: Full-time, fixed term for a period of 2 years. We welcome
-
Design & Verification: Develop and verify RTL code in SystemVerilog/Verilog to ensure robust digital VLSI design. Optimization & Physical Implementation: Drive the process from synthesis through place-and
-
, Verilog) and familiarity with modern computing architectures. Familiarity with high-performance computing trends. Familiarity with recent advancement in the field of Computer Architecture, more specifically
-
international degree Preferred qualifications PhD in Astronomy, Physics, or Electrical Engineering. Expertise in electronic circuit design Proficiency with: Linux, Python, C, Verilog, VHDL, CUDA, MATLAB, and
-
UltraScale+ RFSoC, Altera Cyclone SoC); Good knowledge of C/C++ and familiarity with Verilog/VHDL HDL and communication between FPGA and CPU cores. The experiment control and automation of routine experimental
-
degree in electronics, electrical engineering or related fields; At least 1-2 years of experience in electronics design is preferred; Experience in programmable digital logic design using Verilog or VHDL
-
degree in electronics, electrical engineering or related fields; At least 1-2 years of experience in electronics design is preferred; Experience in programmable digital logic design using Verilog or VHDL