Sort by
Refine Your Search
-
Listed
-
Country
-
Employer
- Carnegie Mellon University
- National University of Singapore
- Pennsylvania State University
- Fraunhofer-Gesellschaft
- Brookhaven Lab
- Lawrence Berkeley National Laboratory
- University of Southern California
- Autonomous University of Madrid (Universidad Autónoma de Madrid)
- Battelle
- California State University San Marcos
- Delft University of Technology (TU Delft)
- Forschungszentrum Jülich
- International Iberian Nanotechnology Laboratory (INL)
- Johnson & Wales University
- Max Planck Institute of Molecular Cell Biology and Genetics, Dresden
- National University of Science and Technology POLITEHNICA Bucharest
- North Carolina State University
- Princeton University
- Purdue University
- Radix Trading LLC
- Ulster University
- University of California
- University of Michigan
- University of Texas at Austin
- University of Utah
- Virginia Tech
- Warsaw University of Technology
- Woods Hole Oceanographic Institution
- Yale University
- 19 more »
- « less
-
Field
-
that emerge. Analyze FPGA hardware and software interface specifications described via VHDL or Verilog to ensure it meets system requirements. Analyze software test and evaluation techniques and methodologies
-
interface specifications described via VHDL or Verilog to ensure it meets system requirements. Analyze software test and evaluation techniques and methodologies. Analyze static, dynamic and complexity
-
FPGA hardware and software interface specifications described via VHDL or Verilog to ensure it meets system requirements. Analyze software test and evaluation techniques and methodologies. Analyze static
-
mitigate those that emerge. Analyze FPGA hardware and software interface specifications described via VHDL or Verilog to ensure it meets system requirements. Analyze software test and evaluation techniques
-
verbal communication skills. Experienced professional with expertise in RTL design (Verilog, SystemVerilog, VHDL), IP integration, simulation, timing closure, and hardware deployment. Proficient in C/C
-
, or Matlab/Octave. Strong written and verbal communication skills. Experienced professional with expertise in RTL design (Verilog, SystemVerilog, VHDL), IP integration, simulation, timing closure, and hardware
-
California State University San Marcos | San Marcos, California | United States | about 17 hours ago
or Verilog Programming for Xilinx, or an engineering class Electrical Engineering industry or research experience Experience with ABET reporting Demonstrated commitment to actively engaging undergraduates in
-
UltraScale+ RFSoC, Altera Cyclone SoC); Good knowledge of C/C++ and familiarity with Verilog/VHDL HDL and communication between FPGA and CPU cores. The experiment control and automation of routine experimental
-
towards a better solution > Proficiency with Python for unit testing > Experience coding in VHDL /verilog > Used Xilnix and/or Altera FPGAs > Familiar with Modelsim > Previously worked on large FPGA stratix
-
(requirements, design, implementation and test) of FPGA Design and/or ASIC Design. Knowledge of SystemVerilog, Verilog and/or VHDL. Experience with verification languages (UVM, SystemVerilog, SystemC). Expertise