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measure power and delay. Required Qualifications Experience in Verilog, Cadence Virtuoso, synthesis, and RTL design. Desired Qualifications Excellent communication skills. Special Instructions to Applicants
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, methodologies, tools, and techniques to prevent risks and issues, and mitigate those that emerge. Analyze FPGA hardware and software interface specifications described via VHDL or Verilog to ensure it meets
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, signal filtering, power filtering, PLLs, RF circuits, medium-speed digital, etc. Basic familiarity with small, low-power FPGAs and Verilog. Linux experience a plus. Demonstrate experience in schematic
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target and accelerator research. Development and implementation of software based on programming languages C, Python, and programming languages for FPGAs, including VDHL and Verilog. Train and support
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-Level Synthesis (HLS) implementations. Working knowledge of C++/C, Python, Verilog. Motivated self-starter with the ability to work independently and to participate creatively in collaborative teams
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. Demonstrated programming experience in Python and C/C++ or Verilog, SystemVerilog. Excellent oral and written communication skills. Ability to work productively independently and collaboratively as part of a
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Python and C/C++ or Verilog, SystemVerilog. Excellent oral and written communication skills. Ability to work productively independently and collaboratively as part of a multidisciplinary team. Desired
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accelerator applications, especially storage ring lattice and orbit control. Proficient in RTL design (Verilog/SystemVerilog/VHDL), IP integration, simulation, timing closure, and FPGA deployment. Skilled in C
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to prevent risks and issues, and mitigate those that emerge. Analyze FPGA hardware and software interface specifications described via VHDL or Verilog to ensure it meets system requirements. Analyze software
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or Verilog Programming for Xilinx, or an engineering class Electrical Engineering industry or research experience Experience with ABET reporting Demonstrated commitment to actively engaging undergraduates in