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mitigate those that emerge. Analyze FPGA hardware and software interface specifications described via VHDL or Verilog to ensure it meets system requirements. Analyze software test and evaluation techniques
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technical communication skills. Preferred Qualifications: Experience with Xilinx FPGA development tools (Vivado) and Hardware Description Languages such as Verilog and/or VHDL. Experience with using
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Languages such as Verilog and/or VHDL. • Experience with using instrumentation to test, characterize, and debug high-speed analog and digital electronics, including FPGAs and RF. • Familiarity with digital
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, or related field. You have proficiency in one or more of the following: C, C++, VHDL, Verilog, Python, C#. You’ve built, analyzed, debugged, and/or tested bare-metal systems and are familiar with a CMSIS/HAL
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circuit design experience preferred Know how to design circuit using one or more of the software listed (Cadence; Fluent use of LT-Spice, Verilog-A, Python, ADS, ICCAP, etc.) Know how to perform circuit
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, or Matlab/Octave. Strong written and verbal communication skills. Experienced professional with expertise in RTL design (Verilog, SystemVerilog, VHDL), IP integration, simulation, timing closure, and hardware
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experience includes using MATLAB, GNU Radio, HDL Coder, REDHAWK, XMIDAS, VHDL/Verilog, C++, and/or Python for RF spectrum access applications. (2) Foundation in quantum mechanics, with additional emphases
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towards a better solution > Proficiency with Python for unit testing > Experience coding in VHDL /verilog > Used Xilnix and/or Altera FPGAs > Familiar with Modelsim > Previously worked on large FPGA stratix
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or Verilog Programming for Xilinx, or an engineering class Electrical Engineering industry or research experience Experience with ABET reporting Demonstrated commitment to actively engaging undergraduates in
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sponsorship of an employment visa for this opportunity. Knowledge, Skills, and Abilities A published track record of conducting research and applying scientific methods. Mastery of C/C++, Python, Verilog/VHDL