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background (e.g. Python, C/C++, VHDL/Verilog) and a motivation to work across disciplines. You are a team player with good written and spoken English communication skills, a willingness to contribute to
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-level knowledge in FPGA/hardware design using hardware description languages and/or high-level synthesis (VHDL, Verilog, Vitis HLS, Vitis), and experience in programming FPGA boards. You have basic
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Design & Verification: Develop and verify RTL code in SystemVerilog/Verilog to ensure robust digital VLSI design. Optimization & Physical Implementation: Drive the process from synthesis through place-and
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, Verilog) and familiarity with modern computing architectures. Familiarity with high-performance computing trends. Familiarity with recent advancement in the field of Computer Architecture, more specifically