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of embedded machine learning, neuromorphic hardware and deep learning accelerators. Want to get more information? Click here. What you will do Responsible for writing Verilog/ VHDL code for AI blocks Perform
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, information technology or comparable with a master's or diploma degree Good knowledge in analog circuit design methodologies and signal integrity analysis Fundamental expertise in working with Verilog AMS
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of embedded machine learning, neuromorphic hardware and deep learning accelerators. Want to get more information? Click here. What you will do Responsible for RTL design (VHDL, Verilog) of digital blocks and
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circuit description (VHDL or Verilog) and programming (C/C++, Python) Conceptual knowledge of network-on-chips and RISC-V processor cores Good English capabilities and preferably good knowledge of German
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modules using Verilog or VHDL for mixed-signal accelerators and testing structures Develop and maintain testbenches for RTL verification; ensure functional coverage and efficient debugging Support FPGA
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discipline Knowledge of Verilog or VHDL Programming skills in C/C++ Independent and self-organizing work style, as well as enjoyment of working in an international environment Good German and/or good
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Max Planck Institute of Molecular Cell Biology and Genetics, Dresden | Dresden, Sachsen | Germany | 2 months ago
hardware description language (VHDL, Verilog, …). Our offer Salary corresponding to qualification and experience according to TVöD Bund (German civil service tariff). The initial contract is for 2 years with
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charge pump topologies at 4k. Behavioural modelling in Verilog-A. Transistor level design and verification through simulation. Layout of the charge pump and post layout verification. Documentation and