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27 Jan 2026 Job Information Organisation/Company University of Siegen Department Embedded Systems Research Field Computer science » Computer architecture Researcher Profile First Stage Researcher
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Helmholtz-Zentrum Dresden-Rossendorf - HZDR - Helmholtz Association | Gorlitz, Sachsen | Germany | 18 days ago
implementation of advanced algorithms, including variational and optimization-based approaches # Investigation and adaptation of mathematical methods in hybrid classical–quantum computing contexts # Documentation
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the Unconventional Communications and Computing Laboratory (UC2), led by Dr Michael T. Barros, which develops modelling and algorithmic methods for networked communication and computation under real-world constraints
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working at the intersection of machine learning, algorithmic fairness, human-computer interaction, and responsible AI. The project aims to investigate how bias emerges in data pipelines and AI systems
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and Machine Learning, with a focus on studying geometric structures in data and models and how to leverage such structure for the design of efficient machine learning algorithms with provable guarantees
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Germany Type of Contract To be defined Job Status Other Is the job funded through the EU Research Framework Programme? Not funded by a EU programme Is the Job related to staff position within a Research
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: Manchester Employment type: Fixed Term Division/Team: Department of Computer Science Hours Per Week: 1 FTE Closing date (DD/MM/YYYY): 02/02/2026 Contract Duration: 24 months School/Directorate: School
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to contribute to our projects in areas such as: Network Security, Information Assurance, Model-driven Security, Cloud Computing, Cryptography, Satellite Systems, Vehicular Networks, and ICT Services
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/or experience with large-scale data analysis, algorithm development, or computational modeling. Required Qualifications: Doctoral degree in linguistics, cognitive science, psychology, hearing and
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conventional embedded platforms as well as unconventional compute technologies. Designing and simulating controllers that balance high performance with hardware efficiency Mapping your algorithms to hardware and