34 machine-learning "https:" "https:" "https:" "https:" "https:" "https:" "Imperial College London" positions at Instituto Superior Técnico in Portugal
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22 Jan 2026 Job Information Organisation/Company Instituto Superior Técnico Department Direção de Recursos Humanos Research Field Engineering » Computer engineering Researcher Profile First Stage
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to monitoring cracking in concrete bridges and viaducts through computer vision The work is supported by BRISA and will use as case study the viaduct over the Rio de Anços on the A1. Duration: 6 months Maximum
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platform of the Instituto Superior Técnico at https://fenix.tecnico.ulisboa.pt/fenixedu-admissions and requires registration and validation of the candidate's identity. Applications are only accepted when
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can be viewed in the admissions platform. The results Where to apply Website https://fenix.tecnico.ulisboa.pt/fenixedu-admissions Requirements Research FieldEngineering » Computer engineeringEducation
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Superior Técnico at https://fenix.tecnico.ulisboa.pt/fenixedu-admissions and requires registration and validation of the candidate's identity. Applications are only accepted when the form available in
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the computer network. Duration: 12 months, not renewed. Applications must be exclusively submitted on the admissions platform of the Instituto Superior Técnico at https://fenix.tecnico.ulisboa.pt
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to candidates with knowledge of Python programming. Applications must be exclusively submitted on the admissions platform of the Instituto Superior Técnico at https://fenix.tecnico.ulisboa.pt/fenixedu-admissions
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12 Dec 2025 Job Information Organisation/Company Instituto Superior Técnico Department Direção de Recursos Humanos Research Field Engineering » Computer engineering Researcher Profile First Stage
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26 Nov 2025 Job Information Organisation/Company Instituto Superior Técnico Department Direção de Recursos Humanos Research Field Engineering » Computer engineering Researcher Profile First Stage
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Verilog description. Work Plan - Become familiar with the design flow in Workcraft - Become familiar with Signal Transition Graph (STG) design - Become familiar with specifying state machines in Verilog