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of embedded machine learning, neuromorphic hardware and deep learning accelerators. Want to get more information? Click here. What you will do Responsible for RTL design (VHDL, Verilog) of digital blocks and
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RTL design for digital blocks, including design, synthesis, and timing closure Work independently in various phases of the RTL-to-GDS flow: focusing on hierarchical floor planning placement, clock tree
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control systems, designing RTL modules, writing testbenches and integrating these into larger systems, with a focus on performance and efficiency for AI applications. What you will do Design and develop RTL
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wide range of markets such as automotive, industrial and aerospace. Not all aspects of verification and validation can be adequately covered by purely RTL-based simulations. Specifically, demonstrating
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; currently enrolled in Master’s/Diploma in electrical engineering or related field Basic understanding of in-memory computing and neural networks Interest in digital design and being familiar with RTL concepts