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of FPGA designs, including timing analysis, code coverage and coding rule checks Support FPGA integration on target hardware Create design documentation in compliance with internal and external normative
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applications for a PhD position (m/f/d, E13 TV-L, 66%) The position is expected to be filled from the 1st of June 2025 and the appointment will be for 3 years. The position is a “wissenschaftliche
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of ASIC/ FPGA SoC architecture and digital design Proficiency in hardware description languages such as System Verilog, Verilog, or VHDL Programming knowledge in Python and C Experience on frontend and
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to planned ²²⁹Thorium ion spectroscopy experiments at GSI. The successful candidate is expected to co-supervise a PhD student working in this project. We are looking for candidates who have: a completed PhD
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engineering Researcher Profile First Stage Researcher (R1) Positions PhD Positions Country Germany Application Deadline 12 May 2025 - 23:00 (Europe/Berlin) Type of Contract Temporary Job Status Full-time Hours