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) and parallel computing, with a focus on cost-efficient and scalable model deployment. Skilled in working with medium-large scale multicore and heterogeneous (CPU + GPU) clusters. Excellent verbal and
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RISC-V ISA. Your project will involve developing and verifying time-predictable on-chip communication to support multicore systems and provide a basis for real-time automotive functionalities
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RISC-V ISA. Your project will be on developing time-predictable RISC-V architectures to support multicore systems as a basis for real-time automotive functionalities. Responsibilities: Conduct research
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optimized code written by expert programmers and can target different hardware architectures (multicore, GPUs, FPGAs, and distributed machines). In order to have the best performance (fastest execution
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hardware architectures (multicore, GPUs, FPGAs, and distributed machines). In order to have the best performance (fastest execution) for a given Tiramisu program, many code optimizations should be applied
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software verification and validation methods and processes, modern software architectures and frameworks, new generation processors and multicores and model-based engineering. The Section also participates