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Lecturer - EE 301: Digital Systems Design with HDL (Spring 2026) Apply now Job no: 552901 Work type: Instructional Faculty - Temporary/Lecturer Location: San Marcos Categories: Unit 3 - CFA
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EE 301: Digital Systems Design with HDL Position: Lecturer - Academic Year Semester: Spring 2026 Days/Times: Varies multiple sections Modality: In-person College: College of Science, Technology
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HDL code of SPARROW (e.g., with logic gates and multiplexers) to simulate transient faults, ideally through automated insertion. Conduct fault injection campaigns on the target hardware platform
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Python and/or MATLAB; familiarity with HDL (VHDL/Verilog) and FPGA design tools, e.g. Xilinx Vivado, Viti, is considered a plus Previous involvement in ESA, EU or other publicly funded research projects
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or equivalent Skills/Qualifications Technical Skills: Digital design, HDL design: VHDL and SystemVerilog. Design with FPGAs. Cadence software: front-end and back-end (Genus, Innovus), Virtuoso. Specific
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. Experience with higher-level hardware design languages (HDLs) such as CHISEL, PyMTL, or others. Experience with FPGA design flows. Demonstrated ability to lead technical efforts with teams of people will also
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of comercial design tools like Cadence / Synopsys. - Competence in computer architectures and digital system design with HDLs (Verilog or VHDL). - Knowledge heterogeneous integration or chiplet design. Currently
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system design with HDLs (Verilog or VHDL). - Knowledge heterogeneous integration or chiplet design. Currently, pursuing a master's degree with specific content on electronic design, the work can be used as
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FunctionsEmpty heading Work on projects involving the structure, composition, and function of high-density lipoproteins (HDL) as well as defining how proteins work together on the surface of triglyceride-rich
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languages (HDL). Proficiency in scientific programming and laboratory automation Experience developing control and analysis software for instrumentation and optical measurements. Strong analytical