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Lecturer - EE 301: Digital Systems Design with HDL (Spring 2026) Apply now Job no: 552901 Work type: Instructional Faculty - Temporary/Lecturer Location: San Marcos Categories: Unit 3 - CFA
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or equivalent Skills/Qualifications Technical Skills: Digital design, HDL design: VHDL and SystemVerilog. Design with FPGAs. Cadence software: front-end and back-end (Genus, Innovus), Virtuoso. Specific
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EE 301: Digital Systems Design with HDL Position: Lecturer - Academic Year Semester: Spring 2026 Days/Times: Varies multiple sections Modality: In-person College: College of Science, Technology
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of comercial design tools like Cadence / Synopsys. - Competence in computer architectures and digital system design with HDLs (Verilog or VHDL). - Knowledge heterogeneous integration or chiplet design. Currently
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system design with HDLs (Verilog or VHDL). - Knowledge heterogeneous integration or chiplet design. Currently, pursuing a master's degree with specific content on electronic design, the work can be used as
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with a CardioChek Plus analyler (for Total Cholesterol, HDL, LDL, TRIG, and Glucose), obtaining a manual blood pressure, and measuring weight body composition Other duties (20%) Complete required
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. Specific Requirements • Competence on computer architectures and digital system design with HDLs (Verilog or VHDL). • Notion on RISC-V ISA and the integration of custom accelerators. Embedded systems
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design and development, with a strong understanding of Verilog, SystemVerlilog and other HDLs. Extensive experience in embedded software development, including C/C++/Rust programming for real-time
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based integrations (FBDI) between third-party systems and Oracle Fusion Cloud using HDL and HSDL. Expert level experience in writing complex SQL queries, SQL tuning and database concepts. Experience
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: Experience with BI Publisher Experience with HCM Extracts HDLs Experience with Spreadsheet loaders Data Mapping Experience with Data Transformation Experience with Data Modeling Experience with Oracle HCM