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Field
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using state-of-the-art techniques. Develop bytecode to test and analyze VHDL for FPGAs and ensure hardware interfaces and controls meet the intended design. Who you are You have a BS in Computer
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platforms, including embedded and edge computing environments (e.g., Jetson, Raspberry Pi, FPGA, neuromorphic chips) Publish results in top-tier journals and present at leading international conferences and
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significant prior experience of: power semiconductor switching converters such as oscilloscopes programming MicroSemi FPGAs in the Libero environment low level programming of embedded C++ in Infineon Tricore
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recommended. Strong background in computer architectures and embedded platforms (ARM Cortex-M, NPU, FPGA, embedded GPU), e.g., via academic courses and/or project courses Research experience (e.g., through a
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contraintes strictes de consommation énergétique (quelques mW maximum) et de dissipation thermique, rendant l'utilisation des circuits conventionnels (FPGAs, DACs/ADCs) inadaptée. Les architectures actuelles
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undergraduate students, and technical personnel at the ElectroScience Laboratory (ESL); Leads and advances research and development on systems requiring the use of Field Programmable Gate Arrays (FPGAs); designs
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Low-power Network Protocols, MAC Layer protocols C/C++, Compilers, Embedded Systems (Optionally) Basic Electronics, PCBs, Circuits, FPGAs Highlights of the position Part of a Marie Skłodowska Curie
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architectures Support lab activities related to designing and optimizing AI implementations across various platforms, including embedded and edge computing environments (e.g., Jetson, Raspberry Pi, FPGA
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detectors, ultra-high vacuum, tritium gas handling, magnetometry, cryogenic engineering, charged-particle trapping, atom trapping and cooling, RF/microwave cavities and radiation detection, FPGAs, Python, C
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Reconfigurable/Spatial computing architectures, such as FPGAs, CGRAs, and AI accelerators, offer significant opportunities for improving performance and energy efficiency compared to traditional CPUs