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into the co-design of ultra-low-power AI hardware architectures tailored for edge computing applications. The research aims to develop neuromorphic processors, FPGA/ASIC-based AI accelerators, and intelligent
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, Computer Science, or related field with excellent grades. Sound knowledge of computer hardware design and synthesis tools (ASIC, FPGA). Good programming and scripting skills. Excellent English communication
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design and synthesis tools (ASIC, FPGA). Good programming and scripting skills. Excellent English communication, presentation, and writing skills. Must be a team player. Knowledge of computing-in-memory is
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synthesis tools (ASIC, FPGA). Good programming and scripting skills. Excellent English communication, presentation, and writing skills. Must be a team player. Knowledge of computing-in-memory is an added
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design and synthesis tools (ASIC, FPGA). Good programming and scripting skills. Excellent English communication, presentation, and writing skills. Must be a team player. Knowledge of computing-in-memory is
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engineering a strong background in digital design, hardware description languages (e.g. Verilog, VHDL, SystemC), reconfigurable architectures (e.g. FPGA, CGRA) What we expect from you: above-average degree
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of FPGA designs, including timing analysis, code coverage and coding rule checks Support FPGA integration on target hardware Create design documentation in compliance with internal and external normative
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interested in PQC, FPGA/processor design, and aerospace cybersecurity. The candidate will join vibrant doctoral community, benefiting from world-class research facilities in the modern Dalton Building. Project
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, SystemC), reconfigurable architectures (e.g. FPGA, CGRA) What we expect from you: above-average degree achieved in short study period willingness and ability to think beyond the boundaries of your field
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at international project meetings. We require a solid interest in digital electronics development, experience in C and python programming and familiarity with Linux environments. Knowledge of FPGA-related workflows