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Field
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ESA projects and carries out technological research and development (R&D) in the field of integrated circuits (ASICs, ASSPs, FPGAs, microprocessors and microcontrollers). Duties Reporting to the Head of
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the following topics: 1)Topic 1 Digital control of DC/DC converters This topic will be hosted in the Power Management and Distribution section in the TEC-EP Division. An FPGA will be used to design a control
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potential for those solutions. Develop architectural and circuit models for emulation in FPGA hardware Develop metrics and benchmark tests in order to compare conventional CMOS based processors/accelerators
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LevelUndergraduate Skills/Qualifications - Conocimientos de programación y uso de sistemas basados en microprocesadores. - Conocimientos de diseño de circuitos digitales para sistemas reconfigurables basados en FPGA
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, such as C or C++, into hardware description languages like Verilog or VHDL. This enables designers to create digital hardware (e.g., ASICs or FPGAs) more efficiently, by working at a higher abstraction
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projects both within the Department and across the university. Your research interests could include embedded systems and FPGA programming, with applications in biomedical, image processing signal
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multidisciplinary team of engineers, scientists, and external partners. Work on embedded systems and FPGA integration for real-world deployment in astronomical infrastructure. About you Tertiary qualification in
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, microcontrollers and FPGA) to include programming of these devices. Specialist skills required in some or all the following: electronic system building and testing, developing new products through concept
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Specific Integrated Circuits (ASIC), Processors (CPU, GPU, VPU and accelerators), Field Programmable Gate Arrays (FPGA) and System-on-Chips (SoCs), as well as Intellectual Property (IP) Core developments for
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design and development Hardware secure electronics Integrated circuit design (both ASIC and FPGA) Optoelectronics Sensor design and verification Sustainable electronics The successful applicant will be