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, such as C or C++, into hardware description languages like Verilog or VHDL. This enables designers to create digital hardware (e.g., ASICs or FPGAs) more efficiently, by working at a higher abstraction
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physics (HEP) detectors, neuromorphic computing, FPGA/ASIC design, and machine learning for edge processing. The successful candidate will work with a multi-institutional and multi-disciplinary team
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Specific Integrated Circuits (ASIC), Processors (CPU, GPU, VPU and accelerators), Field Programmable Gate Arrays (FPGA) and System-on-Chips (SoCs), as well as Intellectual Property (IP) Core developments for
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Qualifications Master’s of Science in Electrical or Computer Engineering. 12 years of experience in digital or system architecture for SoC/FPGA/ASIC designs, with strong exposure to AI, networking, or HPC
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. Nice to have: Practical experience with machine-learning frameworks (e.g., PyTorch). Prior tape-out experience (ASIC or a complex FPGA prototype) and familiarity with the digital back-end flow (synthesis
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hardware instructions. Proficiency of FPGA development tools such as Vivado, Quartus, or similar for prototyping. Preferred Additional Skills: Strong understanding of ASIC/FPGA design flows, including