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topics. Candidates should have some experience working with FPGAs as well as an understanding of computer networks. Experience with both RTL and HLS design is favoured. The ideal candidate would have some
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work within the ADAPTING PEPR project, funded by France 2030 and led by the ANR (French National Research Agency). Within this project, the ASIC team at IETR aims to develop a distributed platform for
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for manufacture. Knowledge of FPGA development and hardware description languages such as SystemVerilog or VHDL, with experience in simulation, synthesis, and implementation considered highly desirable
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software and hardware (knowledge on working with FPGAs and ASICs will be preferred). Achievement of the expected progression within Post Doc and Senior Post Doc is transferable between the Irish HEI’s
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of water treatment processes and laboratory techniques; Ability to prepare technical reports and contribute to scientific writing. Computer Skills: Proficiency in Office/Google Workspace tools; asic data
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. During the project, these modules will be emulated by RF FPGA boards designed at the beginning of the project. The first objective of the project will therefore be to propose a very low cost wireless link
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will be involved in crafting and applying high-accuracy algorithms for a Spiking Neural Network (SNN) processing unit, to be executed on FPGA and ASIC. As a Postdoc, your key responsibilities will be
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hardware architectures (multicore, GPUs, FPGAs, and distributed machines). In order to have the best performance (fastest execution) for a given Tiramisu program, many code optimizations should be applied
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skills in designing advanced neural networks (including Vision Transformers, Graph Convolutional Networks, and Spiking Neural Networks), hardware implementation of algorithms for reconfigurable FPGA
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a suit of fast electronics (FPGA) that will allow the following achievements: 1) To rapidly repeat single-particle experimental dynamical trajectories to gain sufficient counting statistics in order