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of the digital ASIC-design flow is required: logic synthesis, timing analysis, power simulation, logic equivalence, DFT and/or P&R. Knowledge of FPGA-development is a plus. Knowledge of low-power designs is a plus
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No. 1 scholarship grant for scientific training activities at INFN Structure of Roma for the following research topic: “Development and FPGA Implementation of Neural and Traditional Algorithms
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for advanced sensing applications and the design of embedded readout architectures based on FPGAs or microcontrollers for signal acquisition and processing. The activities will include electro-optical and
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Low-power Network Protocols, MAC Layer protocols C/C++, Compilers, Embedded Systems (Optionally) Basic Electronics, PCBs, Circuits, FPGAs Highlights of the position Part of a Marie Skłodowska Curie