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Python and/or MATLAB; familiarity with HDL (VHDL/Verilog) and FPGA design tools, e.g. Xilinx Vivado, Viti, is considered a plus Previous involvement in ESA, EU or other publicly funded research projects
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, microarchitecture, and hardware/software co-design. Experience with RTL design (Verilog/SystemVerilog/VHDL) and integrating TLM with RTL for hybrid simulation environments is a plus. Familiarity with standard
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complete solutions provider that can manage the full product lifecycle – serving start-ups, SMEs and established OEMs as well as universities. Our highly experienced ASIC development team realizes over 600
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and algorithms for event-based fusion of two physically-colocalized event-based and depth vision sensors, simulate and analyse these models, and explore possibilities to realize them in CMOS ASICs
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recommended. Strong background in computer architectures and embedded platforms (ARM Cortex-M, NPU, FPGA, embedded GPU), e.g., via academic courses and/or project courses Research experience (e.g., through a