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position within a Research Infrastructure? No Offer Description What you will do We are seeking a motivated engineer/ experienced ASIC architect to join our innovative team for definition and delivery
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ASIC architect to join our innovative team for definition and delivery of testchips for new technology pathfinding. You will be involved in the definition and design of demonstrator test chips with focus
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complete solutions provider that can manage the full product lifecycle – serving start-ups, SMEs and established OEMs as well as universities. Our highly experienced ASIC development team realizes over 600
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., GNURadio, Matlab, LabView), and/or FPGA development (e.g., VHDL) is a plus. You are a team player and have strong communication skills. You have a high proficiency in oral and written English. You comply
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and algorithms for event-based fusion of two physically-colocalized event-based and depth vision sensors, simulate and analyse these models, and explore possibilities to realize them in CMOS ASICs
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of distributed MIMO, and/or coordinated multi-AP operation (under study in the Wi-Fi 8 standardisation workgroup), using Hardware Description Language on FPGA, based on the open-source openwifi project (https
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recommended. Strong background in computer architectures and embedded platforms (ARM Cortex-M, NPU, FPGA, embedded GPU), e.g., via academic courses and/or project courses Research experience (e.g., through a
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/VHDL/SystemVerilog), logic synthesis, and have exposure to PnR flows (place & route, timing closure, power estimation). You are skilled in modeling and simulation methodologies for exploring PPA