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arrays (VCSELs), and silicon complementary metal-oxide semiconductor (CMOS) electronics. Researchers from MIT, NUS, NTU, A*STAR, Stanford University and University of Illinois form a uniquely qualified
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Open Date for Applications: November 11th, 2025 Closing Date for Applications: December 2nd, 2025, 23h00m (Lisbon Time) Key words: #CMOS #mixedsignaldesign #ICdesign #PDKs Overview The Piteira Research
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performant, CMOS compatible, infrared colloidal quantum dot photodetectors and light emitters exploiting intersubband transitions. The project is focused in the mid and long wave infrared employing colloidal
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management skills. Strong interpersonal and mentoring skills. Advocate for safety and ethics in the workplace. Preferred: Experience with integrated CMOS circuit design, verification, and tapeout in standard
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Inria, the French national research institute for the digital sciences | Paris 15, le de France | France | about 2 months ago
, with a researcher, an engineer, and a doctoral student. Main activities: conduct state-of-the-art research on energy scavenging CMOS and printed electronic circuits design electronics to interface with
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focus on the 7–20 GHz frequency range and will involve both RFIC/CMOS and MMIC implementations. You will have access to state-of-the-art semiconductor technologies and world-class measurement facilities
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have submitted their doctoral thesis before starting in post. The ideal candidate will have a strong experimental background in one or more of the following fields: integrated circuits, GaN, CMOS, active
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, or nanoscale devices Device or circuit modeling (SPICE, Verilog-A, or equivalent) VLSI/architecture (or, Spintronic-CMOS) design for AI systems Hardware-based security primitives Communication and/or language
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CMOS technology can be employed for optimization of the transparency of the Schottky barrier and for promoting performance of Josephson field-effect transistors (JoFETs). With sufficient coherence
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, the charge carrier density in a thin, doped Si region can be controlled, enabling the fabrication of gate-tunable silicide/Si/silicide junctions. Moreover, various techniques from CMOS technology can be